The present invention relates to a semiconductor device including transistors and connection between the transistors for constituting an LSI with high integration and a decreased area.
With the recent development of a semiconductor device with high integration and high performance, there are increasing demands for more refinement of the semiconductor device. The improvement of the conventional techniques cannot follow these demands, and novel techniques are unavoidably introduced in some technical fields. For example, as a method of forming an isolation, the LOCOS isolation method is conventionally adopted in view of its simpleness and low cost. Recently, however, it is considered that a trench buried type isolation (hereinafter referred to as the trench isolation) is more advantageous for manufacturing a refined semiconductor device.
Specifically, in the LOCOS isolation method, since selective oxidation is conducted, the so-called bird""s beak occurs in the boundary with a mask for preventing the oxidation. As a result, the dimension of a transistor is changed because an insulating film of the isolation invades a transistor region against the actually designed mask dimension. This dimensional change is unallowable in the refinement of a semiconductor device after the 0.5 xcexcm generation. Therefore, even in the mass-production techniques, the isolation forming method has started to be changed to the trench isolation method in which the dimensional change is very small. For example, IBM corporation has introduced the trench isolation structure as a 0.5 xcexcm CMOS process for the mass-production of an MPU (IBM Journal of Research and Development, VOL. 39, No. 1/2, 1995, pp. 33-42).
Furthermore, in a semiconductor device mounting elements such as a MOSFET in an active area surrounded with an isolation, an insulating film is deposited on the active area, the isolation and a gate electrode, and a contact hole is formed by partly exposing the insulating film for connection between the active area and an interconnection member on a layer above the insulating film. This structure is known as a very common structure for the semiconductor device.
FIG. 17 is a sectional view for showing the structure of a conventional semiconductor device. In FIG. 17, a reference numeral 1 denotes a silicon substrate, a reference numeral 2b denotes an isolation with a trench isolation structure which is made of a silicon oxide film and whose top surface is flattened so as to be at the same level as the top surface of the silicon substrate 1, a reference numeral 3 denotes a gate oxide film made of a silicon oxide film, a reference numeral 4a denotes a polysilicon electrode working as a gate electrode, a reference numeral 4b denotes a polysilicon interconnection formed simultaneously with the polysilicon electrode 4a, a reference numeral 6 denotes a low-concentration source/drain region formed by doping the silicon substrate with an n-type impurity at a low concentration, a reference numeral 7a denotes an electrode sidewall, a reference numeral 7b denotes an interconnection sidewall, a reference numeral 8 denotes a high-concentration source/drain region formed by doping the silicon substrate with an n-type impurity at a high concentration, a reference numeral 12 denotes an insulating film made of a silicon oxide film, and a reference numeral 13 denotes a local interconnection made of a polysilicon film formed on the insulating film 12.
The local interconnection 13 is also filled within a connection hole 14 formed in a part of the insulating film 12, so as to be contacted with the source/drain region in the active area through the connection hole 14. In this case, the connection hole 14 is formed apart from the isolation 2b by a predetermined distance. In other words, in the conventional layout rule for such a semiconductor device, there is a rule that the edge of a connection hole is previously located away from the boundary between the active area and the isolation region so as to prevent a part of the connection hole 14 from stretching over the isolation 2b even when a mask alignment shift is caused in photolithography (this distance between the connection hole and the isolation is designated as an alignment margin).
However, in the structure of the semiconductor device as shown in FIG. 17, there arise problems in the attempts to further improve the integration for the following reason:
A distance La between the polysilicon electrode 4a and the isolation 2b is estimated as an index of the integration. In order to prevent the connection hole 14 from interfering the isolation 2b as described above, the distance La is required to be 1.2 xcexcm, namely, the sum of the diameter of the connection hole 14, that is, 0.5 xcexcm, the width of the electrode sidewall 7a, that is, 0.1 xcexcm, the alignment margin from the polysilicon electrode 4a, that is, 0.3 xcexcm, and the alignment margin from the isolation 2b, that is, 0.3 xcexcm. A connection hole has attained a more and more refined diameter with the development of processing techniques, and also a gate length has been decreased as small as 0.3 xcexcm or less. Still, the alignment margin in consideration of the mask alignment shift in the photolithography is required to be approximately 0.3 xcexcm. Accordingly, as the gate length and the connection hole diameter are more refined, the proportion of the alignment margin is increased. This alignment margin has become an obstacle to the high integration.
Therefore, attempts have been made to form the connection hole 14 without considering the alignment margin in view of the alignment shift in the photolithography. Manufacturing procedures adopted in such a case will now be described by exemplifying an n-channel MOSFET referring to FIGS. 18(a) through 18(c).
First, as is shown in FIG. 18(a), after forming an isolation 2b having the trench structure in a silicon substrate 1 doped with a p-type impurity (or p-type well), etch back or the like is conducted for flattening so as to place the surfaces of the isolation 2b and the silicon substrate 1 at the same level. In an active area surrounded with the isolation 2b, a gate oxide film 3, a polysilicon electrode 4a serving as a gate electrode, an electrode sidewall 7a, a low-concentration source/drain region 6 and a high-concentration source/drain region 8 are formed. On the isolation 2b are disposed a polysilicon interconnection 4b formed simultaneously with the polysilicon electrode 4a and an interconnection sidewall 7b. At this point, the top surface of the high-concentration source/drain region 8 in the active area is placed at the same level as the top surface of the isolation 2b. Then, an insulating film 12 of a silicon oxide film is formed on the entire top surface of the substrate.
Next, as is shown in FIG. 18(b), a resist film 25a used as a mask for forming a connection hole is formed on the insulating film 12, and the connection hole 14 is formed by, for example, dry etching.
Then, as is shown in FIG. 18(c), the resist film 25a is removed, and a polysilicon film is deposited on the insulating film 12 and within the connection hole 14. The polysilicon film is then made into a desired pattern, thereby forming a local interconnection 13.
At this point, in the case where the alignment margin in view of the mask alignment shift in the formation of the connection hole 14 is not considered in estimating the distance La between the polysilicon electrode 4a and the isolation 2b, a part of the isolation 2b is included in the connection hole 14 when the exposing area of the resist film 25a is shifted toward the isolation 2b due to the mask alignment shift in the photolithography. Through over-etch in conducting the dry etching of the insulating film 12, although the high-concentration source/drain region 8 made of the silicon substrate is not largely etched because of its small etching rate, the part of the isolation 2b included in the connection hole 14 is selectively removed, resulting in forming a recess 40 in part of the connection hole 14. When the recess 40 in the connection hole 14 has a depth exceeding a given proportion to the depth of the high-concentration source/drain region 8, junction voltage resistance can be decreased and a junction leakage current can be increased because the concentration of the impurity in the high-concentration source/drain region 8 is low at that depth.
In order to prevent these phenomena, it is necessary to provide a predetermined alignment margin as is shown in the structure of FIG. 17 so as to prevent the connection hole 14 from interfering the isolation 2b even when the alignment shift is caused in the lithography. In this manner, in the conventional layout rule for a semiconductor device, an alignment margin in view of the mask alignment shift in the photolithography is unavoidably provided.
Furthermore, a distance between the polysilicon electrode 4a and the connection hole 14 is also required to be provided with an alignment margin. Otherwise, the connection hole 14 can interfere the polysilicon electrode 4a due to the fluctuation caused in the manufacturing procedures, resulting in causing electric short-circuit between an upper layer interconnection buried in the connection hole and the gate electrode.
As described above, it is necessary to provide the connection hole 14 with margins for preventing the interference with other elements around the connection hole, which has become a large obstacle to the high integration of an LSI.
Also in the case where a semiconductor device having the so-called salicide structure is manufactured, the following problems are caused due to a recess formed in the isolation:
FIG. 19 is a sectional view for showing an example of a semiconductor device including the conventional trench isolation and a MOSFET having the salicide structure. As is shown in FIG. 19, a trench isolation 105a is formed in a silicon substrate 101. In an active area surrounded with the isolation 105a, a gate insulating film 103a, a gate electrode 107a, and electrode sidewalls 108a on both side surfaces of the gate electrode 107a are formed. Also in the active area, a low-concentration source/drain region 106a and a high-concentration source/drain region 106b are formed on both sides of the gate electrode 107a. A channel stop region 115 is formed below the isolation 105a. Furthermore, in areas of the silicon substrate 101 excluding the isolation 105a and the active area, a gate interconnection 107b made of the same polysilicon film as that for the gate electrode 107a is formed with a gate insulating film 103b sandwiched, and the gate interconnection 107b is provided with interconnection sidewalls 108b on its both side surfaces. On the gate electrode 107a, the gate interconnection 107b and the high-concentration source/drain region 106b, an upper gate electrode 109a, an upper gate interconnection 109b and a source/drain electrode 109c each made of silicide are respectively formed. Furthermore, this semiconductor device includes an interlayer insulating film 111 made of a silicon oxide film, a metallic interconnection 112 formed on the interlayer insulating film 111, and a contact member 113 (buried conductive layer) filled in a connection hole formed in the interlayer insulating film 111 for connecting the metallic interconnection 112 with the source/drain electrode 109c. 
Now, the manufacturing procedures for the semiconductor device including the conventional trench isolation and the MOSFET with the salicide structure shown in FIG. 19 will be described referring to FIGS. 20(a) through 20(e).
First, as is shown in FIG. 20(a), a silicon oxide film 116 and a silicon nitride film 117 are successively deposited on a silicon substrate 101, and a resist film 120 for exposing an isolation region and masking a transistor region is formed on the silicon nitride film 117. Then, by using the resist film 120 as a mask, etching is conducted, so as to selectively remove the silicon nitride film 116 and the silicon oxide film 117, and further etch the silicon substrate 101, thereby forming a trench 104. Then, impurity ions are injected into the bottom of the trench 104, thereby forming a channel stop region 115.
Then, as is shown in FIG. 20(b), a silicon oxide film (not shown) is deposited, and the entire top surface is flattened until the surface of the silicon nitride film 117 is exposed. Through this procedure, a trench isolation 105a made of the silicon oxide film filled in the trench 104 is formed in the isolation region Reiso.
Next, as is shown in FIG. 20(c), after the silicon nitride film 117 and the silicon oxide film 116 are removed, a gate oxide film 103 is formed on the silicon substrate 101, and a polysilicon film 107 is deposited thereon. Then, a photoresist film 121 for exposing areas excluding a region for forming a gate is formed on the polysilicon film 107.
Then, as is shown in FIG. 20(d), by using the photoresist film 121 as a mask, dry etching is conducted, thereby selectively removing the polysilicon film 107 and the gate oxide film 103. Thus, a gate electrode 107a of the MOSFET in the transistor region Refet and a gate interconnection 107b stretching over the isolation 105a and the silicon substrate 101 are formed. After removing the photoresist film 121, impurity ions are injected into the silicon substrate 101 by using the gate electrode 107a as a mask, thereby forming a low-concentration 382 source/drain region 106a. Then, a silicon oxide film 108 is deposited on the entire top surface of the substrate.
Next, as is shown in FIG. 20(e), the silicon oxide film 108 is anisotropically dry-etched, thereby forming electrode sidewalls 108a and interconnection sidewalls 108b on both side surfaces of the gate electrode 107a and the gate interconnection 107b, respectively. At this point, the gate oxide film 103 below the silicon oxide film 108 is simultaneously removed, and the gate oxide film 103 below the gate electrode 107a alone remains. Then, impurity ions are diagonally injected by using the gate electrode 107a and the electrode sidewalls 108a as masks, thereby forming a high-concentration source/drain region 106b. Then, after a Ti film is deposited on the entire top surface, high temperature annealing is conducted, thereby causing a reaction between the Ti film and the components made of silicon directly in contact with the Ti film. Thus, an upper gate electrode 109a, an upper gate interconnection 109b and a source/drain electrode 109c made of silicide are formed.
The procedures to be conducted thereafter are omitted, but the semiconductor device including the MOSFET having the structure as shown in FIG. 19 can be ultimately manufactured. In FIG. 19, the metallic interconnection 112 is formed on the interlayer insulating film 111, and the metallic interconnection 112 is connected with the source/drain electrode 109c through the contact member 113 including a W plug and the like filled in the contact hole.
When the aforementioned trench isolation structure is adopted, the dimensional change of the source/drain region can be suppressed because the bird""s beak, that is, the oxide film invasion of an active area, which is caused in the LOCOS method where a thick silicon oxide film is formed by thermal oxidation, can be avoided. Furthermore, in the procedure shown in FIG. 20(c), the surfaces of the isolation 105a and the silicon substrate 101 in the transistor region Refet are placed at the same level.
In such a semiconductor device having the trench type isolation, however, there arise the following problems:
When the procedures proceed from the state shown in FIG. 20(d) to the state shown in FIG. 20(e), the silicon oxide film 108 is anisotropically etched so as to form the sidewalls 108a and 108b. At this point, over-etch is required. Through this over-etch, the surface of the isolation 105a is removed by some depth.
FIGS. 21(a) and 21(b) are enlarged sectional views around the boundary between the high-concentration source/drain region 106b and the isolation 105a after this over-etch.
As is shown in FIG. 21(a), between the procedures shown in FIGS. 20(d) and 20(e), the impurity ions are diagonally injected so as to form the high-concentration source/drain region 106b. Through this ion injection, the high-concentration source/drain region 106b is formed also below the edge of the isolation 105a because the isolation 105a is previously etched by some depth. Accordingly, the high-concentration source/drain region 106b is brought closer to the channel stop region 115, resulting in causing the problems of degradation of the junction voltage resistance and increase of the junction leakage current.
In addition, as is shown in FIG. 21(b), in the case where the Ti film or the like is deposited on the high-concentration source/drain region 106b so as to obtain the silicide layer through the reaction with the silicon below, the thus formed silicide layer can invade the interface between the silicon substrate 101 and the isolation 105a with ease. As a result, a short-circuit current can be caused between the source/drain electrode 109c made of silicide and the channel stop region 115.
The object of the present invention is improving the structure of an isolation, so as to prevent the problems caused because the edge of the isolation is trenched in etching for the formation of a connection hole or sidewalls.
In order to achieve the object, the invention proposes first and second semiconductor devices and first through third methods of manufacturing a semiconductor device as described below.
The first semiconductor device of this invention in which a semiconductor element is disposed in each of plural active areas in a semiconductor substrate comprises an isolation for surrounding and isolating each active area, the isolation having a top surface at a higher level than a surface of the active area and having a step portion in a boundary with the active area; an insulating film formed so as to stretch over each active area and the isolation; plural holes each formed by removing a portion of the insulating film disposed at least on the active area; plural buried conductive layers filled in the respective holes; and plural interconnection members formed on the insulating film so as to be connected with the respective active areas through the respective buried conductive layers.
Owing to this structure, in the case where a part of or all the holes are formed so as to stretch over the active areas and the isolation due to mask alignment shift in photolithography, a part of the isolation is removed by over-etch for ensuring the formation of the holes. In such a case, even when the top surface of the isolation is trenched to be lower than the surface of the active area, the depth of the holes formed in the isolation is small in the boundary with the active area because of the level difference between the top surface of the isolation and the surface of the active area. Accordingly, degradation of the junction voltage resistance and increase of the junction leakage current can be suppressed. Therefore, there is no need to provide a portion of the active area where each hole is formed with an alignment margin for avoiding the interference with the isolation caused by the mask alignment shift in the lithography. Thus, the area of the active area can be decreased, resulting in improving the integration of the semiconductor device.
In the first semiconductor device, at least a part of the plural holes can be formed so as to stretch over the active area and the isolation due to fluctuation in manufacturing procedures.
In other words, even when no margin for the mask alignment in the lithography is provided, the problems caused in the formation of the holes can be avoided.
Furthermore, the angle between a side surface of the step portion and the surface of the active area is preferably 70 degrees or more.
As a result, when the hole interferes the isolation, the part of the isolation included in the hole is definitely prevented from being etched through over-etch in the formation of the holes down to a depth where the impurity concentration is low in the active area.
The isolation is preferably a trench isolation made of an insulating material filled in a trench formed by trenching the semiconductor substrate by a predetermined depth.
This is because no bird""s beak is caused in the trench isolation differently from a LOCOS film as described above, and hence, the trench isolation is suitable particularly for the high integration and refinement of the semiconductor device.
In the first semiconductor device, when the semiconductor element is a MISFET including a gate insulating film and a gate electrode formed on the active area; and source/drain regions formed in the active area on both sides of the gate electrode, the following preferred embodiments can be adopted:
The semiconductor device can further comprise a gate interconnection made of the same material as that for the gate electrode and formed on the isolation, each of the holes can be formed on an area including the source/drain region, the isolation and the gate interconnection, and the plural interconnection members can be connected with the gate interconnection on the isolation.
Owing to this configuration, in the case where the interconnection members work as local interconnections for connecting a gate interconnection on the isolation with the active area, there is no need to separately form holes in the insulating film on the gate interconnection and the insulating film on the active area. In addition, there is no need to provide the separate holes with alignment margins from the boundary between the active area and the isolation. Accordingly, the area of the isolation can also be decreased, resulting in largely improving the integration of the semiconductor device.
The semiconductor device can further comprise electrode sidewalls made of an insulating material and formed on both side surfaces of the gate electrode; and a step sidewall made of the same material as the insulating material for the electrode sidewalls and formed on the side surface of the step portion. In this semiconductor device, at least a part of the holes can be formed by also removing a portion of the insulating film disposed on the step sidewall.
Owing to this structure, the abrupt level difference between the surfaces of the isolation and the active area can be released by the step sidewall. Therefore, a residue is scarcely generated in patterning the interconnection members, and an upper interconnection is prevented from being disconnected and increasing in its resistance.
The semiconductor device can further comprise a gate protection film formed on the gate electrode, and at least a part of the holes can be formed so as to stretch over the source/drain region and at least a part of the gate protection film.
Owing to this structure, a part of the gate protection film included in the hole is removed by the over-etch in the formation of the holes. However, the gate electrode is protected by the gate protection film, and hence, electrical short circuit between the gate electrode and the interconnection member can be prevented. Accordingly, there is no need to provide an alignment margin from the gate electrode in the area where each hole is formed, resulting in further improving the integration.
The interconnection members can be first layer metallic interconnections, and the insulating film can be an interlayer insulating film disposed between the semiconductor substrate, and the first layer metallic interconnections. In this case, the semiconductor device preferably further comprises, between the interlayer insulating film and the semiconductor substrate an underlying film made of an insulating material having high etching selectivity against the interlayer insulating film.
The second semiconductor device of this invention in which a semiconductor element is disposed in each of plural active areas in a semiconductor substrate comprises a trench isolation for isolating and surrounding each active area, the trench isolation having a top surface at a higher level than a surface of the active area and having a step portion in a boundary with the active area; and a step sidewall formed on the side surface of the step portion of the trench isolation.
Owing to this structure, in the impurity ion injection for the formation of an impurity diffused layer of the semiconductor device, the step sidewall disposed at the edge of the trench isolation can prevent the impurity ions from being implanted below the edge of the isolation. Furthermore, also in adopting the structure including a source/drain electrode made of silicide, the step sidewall can prevent the silicide layer from being formed at a deep portion. Therefore, a short circuit current can be prevented from occurring between the source/drain electrode and a substrate region such as the channel stop region. In this manner, the function of the trench isolation to isolate each semiconductor element can be prevented from degrading.
In the second semiconductor device, the step sidewall is preferably made of an insulating material.
Also in the second semiconductor device, the semiconductor element can be a MISFET including a gate insulating film and a gate electrode formed on the active area; and source/drain regions formed in the active area on both sides of the gate electrode. This semiconductor device can be further provided with electrode sidewalls formed on both side surfaces of the gate electrode, and the step sidewall can be formed simultaneously with the electrode sidewalls.
Owing to this structure, the semiconductor elements can be a MISFET having the LDD structure suitable for the refinement. Because of this structure together with the trench isolation structure, the semiconductor device can attain a structure particularly suitable for the refinement and the high integration.
The first method of manufacturing a semiconductor device in which a semiconductor element is disposed in each of plural active areas in a semiconductor substrate comprises a first step of forming an isolation in a part of the semiconductor substrate, the isolation having a top surface at a higher level than a surface of the semiconductor substrate and having a step portion in a boundary with the surface of the semiconductor substrate; a second step of introducing an impurity at a high concentration into each active area of the semiconductor substrate surrounded by the isolation; a third step of forming an insulating film on the active area and the isolation; a fourth step of forming, on the insulating film, a masking member having an exposing area above an area at least including a portion of the active area where the impurity at the high concentration is introduced; a fifth step of conducting etching by using the masking member so as to selectively remove the insulating film and form holes; and a sixth step of forming a buried conductive layer by filling the holes with a conductive material and forming, on the insulating film, interconnection members to be connected with the buried conductive layer. In this method, in the fourth step, an alignment margin is not provided for preventing the exposing area of the masking member from including a portion above the isolation when mask shift is caused in photolithography.
In adopting this method, even when a part of the isolation is removed by over-etch in the fifth step so that the top surface of the isolation is etched to be lower than the surface of the active area, the depth of the holes formed in the isolation is small because of the level difference between the isolation and the active area. Accordingly, the decrease of the junction voltage resistance and the increase of the junction leakage current can be suppressed in the manufactured semiconductor device. In addition, the area of the active area can be decreased because no alignment margin from the isolation is provided, resulting in improving the integration of the manufactured semiconductor device.
In the first method of manufacturing a semiconductor device, the following preferred embodiments can be adopted:
The fifth step is preferably performed so as to satisfy the following inequality:
OExc3x97axc3x97(ER2/ER1)xe2x89xa6b+Dxc3x97(2/10) 
wherein xe2x80x9caxe2x80x9d indicates a thickness of the insulating film, xe2x80x9cbxe2x80x9d indicates a level difference between the surface of the active area and the top surface of the isolation, xe2x80x9cER1xe2x80x9d indicates an etching rate of the insulating film, xe2x80x9cER2xe2x80x9d indicates an etching rate of the isolation, xe2x80x9cDxe2x80x9d indicates a depth of an impurity diffused layer in the active area, and xe2x80x9cOExe2x80x9d indicates an over-etch ratio of the insulating film.
In adopting this method, even when a part of the isolation included in the hole is removed by over-etch in the formation of the holes, the bottom of the etched portion does not reach a portion where the impurity concentration is low in the active area. In other words, the top surface of the isolation is never placed at a lower level than the surface of the active area. Accordingly, the degradation of the junction voltage resistance and the increase of the junction leakage current can be definitely prevented in the manufactured semiconductor device.
When the semiconductor element is a MISFET, the method can further include, before the second step, a step of forming a gate insulating film on the active area, a step of depositing a conductive film on the gate insulating film and a step of forming a gate electrode by patterning the conducive film, and in the second step, the impurity at the high concentration is introduced so as to form a source/drain region. In such a case, the following preferred embodiments can be adopted.
The method can further comprise, after the step of depositing the conductive film, a step of depositing a protection insulating film on the conductive film, and in the step of forming the gate electrode, the conductive film as well as the protection insulating film are patterned, so as to form a gate protection film on the gate electrode. The fifth step can be performed so as to satisfy the following inequality:
OExc3x97axc3x97(ER3/ER1) less than c 
wherein xe2x80x9caxe2x80x9d indicates a thickness of the insulating film, xe2x80x9ccxe2x80x9d indicates a thickness of the gate protection film, xe2x80x9cER1xe2x80x9d indicates an etching rate of the insulating film, xe2x80x9cER3xe2x80x9d indicates an etching rate of the gate protection film and xe2x80x9cOExe2x80x9d indicates an over-etch ratio of the insulating film.
When this method is adopted, while the area of the active area is decreased by not providing an alignment margin for avoiding the interference between the connection hole and the gate electrode, the hole is prevented from reaching the gate electrode below the gate protection film.
In the fourth step, the masking member can be formed to be positioned without providing a margin for preventing the exposing area thereof from including a portion above the gate protection film even when the mask shift is caused in the photolithography.
Alternatively, in the fourth step, the masking member can be formed to be positioned with the exposing area thereof including at least a part of a portion above the gate protection film when the mask shift is not caused in the photolithography.
In the third step, an interlayer insulating film can be formed as the insulating film, and in the sixth step, first layer metallic interconnections can be formed as the interconnection members. In such a case, it is preferred that the interlayer insulating film is formed in the third step after an underlying film made of an insulating material having high etching selectivity against the interlayer insulating film is formed below the interlayer insulating film.
The second method of manufacturing a semiconductor device of this invention comprises a first step of forming an underlying insulating film on a semiconductor substrate; a second step of depositing an etching stopper film on the underlying insulating film; a third step of forming a trench by exposing a portion of the etching stopper film and the underlying insulating film where an isolation is to be formed and etching the semiconductor substrate in the exposed portion; a fourth step of depositing an insulating film for isolation on an entire top surface of the substrate, flattening the substrate until at least a surface of the etching stopper film is exposed, and forming a trench isolation in the trench so as to surround a transistor region; a fifth step of removing, by etching, at least the etching stopper film and the underlying insulating film, so as to expose a step portion between the transistor region and the trench isolation; a sixth step of depositing a gate oxide film and a conductive film on the substrate and making the conductive film into a pattern of at least a gate electrode; a seventh step of depositing an insulating film for sidewalls on the entire top surface of the substrate and anisotropically etching the insulating film for the sidewalls, so as to form electrode sidewalls and a step sidewall on side surfaces of the gate electrode and the step portion, respectively; and an eighth step of introducing an impurity into the semiconductor substrate in the transistor region on both sides of the gate electrode, so as to form source/drain regions.
When this method is adopted, since the step sidewall is formed between the semiconductor substrate in the transistor region and the trench isolation after completing the fifth step, the impurity ions are prevented from being implanted below the edge of the trench isolation in the impurity ion injection in the eighth step. Furthermore, also when an area in the vicinity of the surface of the source/drain region is subsequently silicified, the step sidewall made of the insulating film can prevent the silicide layer from being formed at a deep portion. Accordingly, not only the degradation of the junction voltage resistance and the current leakage but also the occurrence of a short circuit current between the source/drain electrode and the substrate region such as the channel stop region can be prevented.
In the second method of manufacturing a semiconductor device, the following preferred embodiments can be adopted:
In the second step, the thickness of the etching stopper film is preferably determined in consideration of an amount of over-etch in the seventh step, so that the step portion having a level difference with a predetermined size or more is exposed in the fifth step.
The method can further comprise, after completing the eighth step, a step of silicifying at least an area in the vicinity of the surface of the source/drain region.
The third method of manufacturing a semiconductor device of this invention comprises a first step of forming a gate insulating film on a semiconductor substrate; a second step of depositing a first conductive film to be formed into a gate electrode on the gate insulating film; a third step of forming a trench by exposing a portion of the first conductive film where a trench isolation is to be formed and etching the semiconductor substrate in the exposed portion; a fourth step of depositing an insulating film for isolation on an entire top surface of the substrate, flattening the substrate at least until a surface of the first conductive film is exposed, and forming the trench isolation in the trench so as to surround a transistor region; a fifth step of depositing a second conductive film to be formed into at least an upper gate electrode on the entire top surface of the flattened substrate; a sixth step of making the first and second conductive films into a pattern at least of the gate electrode and exposing a step portion between the transistor region and the trench isolation; a seventh step of depositing an insulating film for sidewalls on the entire top surface of the substrate and anisotropically etching the insulating film for the sidewalls, so as to form electrode sidewalls and a step sidewall on side surfaces of the gate electrode and the step portion, respectively; and an eighth step of introducing an impurity into the semiconductor substrate in the transistor region on both sides of the gate electrode, so as to form source/drain regions.
When this method is adopted, the same effects as those attained by the second method of manufacturing a semiconductor device can be attained. In addition, in the patterning process for the gate electrode, the top surface of the substrate is completely flat, and hence, the patterning accuracy for the gate electrode can be improved.